Initial Import Conversion
This commit is contained in:
Elizabeth Cray
1
Appletini/PCB_v1.kicad_dru
Normal file
1
Appletini/PCB_v1.kicad_dru
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@@ -0,0 +1 @@
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(version 1)
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7294
Appletini/PCB_v1.kicad_pcb
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7294
Appletini/PCB_v1.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
175
Appletini/PCB_v1.kicad_pro
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175
Appletini/PCB_v1.kicad_pro
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@@ -0,0 +1,175 @@
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{
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||||
"board": {
|
||||
"design_settings": {
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||||
"defaults": {
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||||
"board_outline_line_width": 0.049999999999999996,
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||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
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||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
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||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
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||||
"pads": {
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||||
"drill": 0.762,
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||||
"height": 1.524,
|
||||
"width": 1.524
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||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
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||||
"zones": {
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||||
"45_degree_only": false,
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||||
"min_clearance": 0.508
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||||
}
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||||
},
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||||
"diff_pair_dimensions": [],
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||||
"drc_exclusions": [],
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"meta": {
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||||
"filename": "board_design_settings.json",
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||||
"version": 2
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||||
},
|
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"rule_severities": {
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||||
"annular_width": "error",
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||||
"clearance": "error",
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||||
"copper_edge_clearance": "error",
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||||
"courtyards_overlap": "error",
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||||
"diff_pair_gap_out_of_range": "error",
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||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
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||||
"duplicate_footprints": "warning",
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||||
"extra_footprint": "warning",
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||||
"footprint_type_mismatch": "error",
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||||
"hole_clearance": "error",
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||||
"hole_near_hole": "error",
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||||
"invalid_outline": "error",
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||||
"item_on_disabled_layer": "error",
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||||
"items_not_allowed": "error",
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||||
"length_out_of_range": "error",
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||||
"malformed_courtyard": "error",
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||||
"microvia_drill_out_of_range": "error",
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||||
"missing_courtyard": "ignore",
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||||
"missing_footprint": "warning",
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||||
"net_conflict": "warning",
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||||
"npth_inside_courtyard": "ignore",
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||||
"padstack": "error",
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||||
"pth_inside_courtyard": "ignore",
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||||
"shorting_items": "error",
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||||
"silk_over_copper": "warning",
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||||
"silk_overlap": "warning",
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||||
"skew_out_of_range": "error",
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||||
"through_hole_pad_without_hole": "error",
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||||
"too_many_vias": "error",
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||||
"track_dangling": "warning",
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||||
"track_width": "error",
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||||
"tracks_crossing": "error",
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||||
"unconnected_items": "error",
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||||
"unresolved_variable": "error",
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||||
"via_dangling": "warning",
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||||
"zone_has_empty_net": "error",
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||||
"zones_intersect": "error"
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||||
},
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
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||||
"allow_microvias": false,
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||||
"max_error": 0.005,
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||||
"min_clearance": 0.15239999999999998,
|
||||
"min_copper_edge_clearance": 0.07619999999999999,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
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||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
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||||
"zones_allow_external_fillets": false,
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||||
"zones_use_no_outline": true
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||||
},
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||||
"layer_presets": []
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||||
},
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||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
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||||
},
|
||||
"libraries": {
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||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
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||||
},
|
||||
"meta": {
|
||||
"filename": "PCB_v1.kicad_pro",
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||||
"version": 1
|
||||
},
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||||
"net_settings": {
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||||
"classes": [
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||||
{
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||||
"bus_width": 12.0,
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||||
"clearance": 0.1524,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
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||||
"meta": {
|
||||
"version": 2
|
||||
},
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||||
"net_colors": null
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||||
},
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||||
"pcbnew": {
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||||
"last_paths": {
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||||
"gencad": "",
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||||
"idf": "",
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||||
"netlist": "",
|
||||
"specctra_dsn": "",
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||||
"step": "",
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||||
"vrml": ""
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||||
},
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||||
"page_layout_descr_file": ""
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||||
},
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||||
"schematic": {
|
||||
"legacy_lib_dir": "",
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||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
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||||
181
Appletini/PCB_v1.pretty/057-050-1.kicad_mod
Normal file
181
Appletini/PCB_v1.pretty/057-050-1.kicad_mod
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@@ -0,0 +1,181 @@
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(footprint "057-050-1" (version 20211014) (generator pcbnew)
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(layer "F.Cu")
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(tedit 0)
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(descr "<b>CONNECTOR</b><p>\nseries 057 contact pc board low profile headers<p>\nstraight")
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(fp_text reference "REF**" (at -30.46 6.88) (layer "F.SilkS")
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||||
(effects (font (size 1.63576 1.63576) (thickness 0.14224)) (justify left bottom))
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||||
(tstamp a447579b-0127-4c97-9319-249885b1fd82)
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||||
)
|
||||
(fp_text value ">VALUE" (at -31.21 -4.55) (layer "F.SilkS")
|
||||
(effects (font (size 1.63576 1.63576) (thickness 0.14224)) (justify left bottom))
|
||||
(tstamp b591be8a-a021-442a-a188-36bee9d61b41)
|
||||
)
|
||||
(fp_line (start 1.9 3.32) (end 1.9 4.03) (layer "F.SilkS") (width 0.2032) (tstamp 2a411983-1e0e-4cd4-9054-ebd16076264b))
|
||||
(fp_line (start -34.81 3.3) (end -34.81 -3.3) (layer "F.SilkS") (width 0.2032) (tstamp 3b7549f8-0b3b-4b83-8410-b5f7e24c08ee))
|
||||
(fp_line (start -31.5 1.97) (end -32.9 1.97) (layer "F.SilkS") (width 0.4064) (tstamp 4de6ec3d-d5e4-4149-a391-2fcea03cf2ec))
|
||||
(fp_line (start -32.9 1.97) (end -32.2 3.04) (layer "F.SilkS") (width 0.4064) (tstamp 57b7bd54-9c18-411a-a4a4-8609c3d6b9e9))
|
||||
(fp_line (start -1.9 3.3) (end -34.81 3.3) (layer "F.SilkS") (width 0.2032) (tstamp 59eae2a3-677e-4ed7-9231-a0801c6fffea))
|
||||
(fp_line (start 34.81 -3.3) (end 34.81 3.3) (layer "F.SilkS") (width 0.2032) (tstamp 60a04abf-ea96-43a1-9d4a-783217675b6c))
|
||||
(fp_line (start -1.9 3.32) (end -1.9 4.03) (layer "F.SilkS") (width 0.2032) (tstamp 6248da0f-8b03-4889-9e75-82b0c9bcd8c4))
|
||||
(fp_line (start 34.81 3.3) (end 35.61 4.1) (layer "F.SilkS") (width 0.2032) (tstamp 64d43608-59ab-4deb-a448-f748f96d5a22))
|
||||
(fp_line (start -32.2 3.04) (end -31.5 1.97) (layer "F.SilkS") (width 0.4064) (tstamp 730b1c7d-3c66-4bf4-8d2a-44577bcee7a5))
|
||||
(fp_line (start -35.61 4.1) (end -35.61 -4.1) (layer "F.SilkS") (width 0.2032) (tstamp 7e4a365e-1f00-4ceb-84cb-a8f223a1570a))
|
||||
(fp_line (start 35.61 4.1) (end 35.61 -4.1) (layer "F.SilkS") (width 0.2032) (tstamp 858378e5-8878-4088-be98-e86acb2b51c3))
|
||||
(fp_line (start -35.61 -4.1) (end -34.81 -3.3) (layer "F.SilkS") (width 0.2032) (tstamp 92b81557-9a18-4a80-aeea-eaf38d73ae35))
|
||||
(fp_line (start 35.61 -4.1) (end 34.81 -3.3) (layer "F.SilkS") (width 0.2032) (tstamp a292b99d-9fb1-408a-aaa4-033a8ed320d6))
|
||||
(fp_line (start -34.81 -3.3) (end 34.81 -3.3) (layer "F.SilkS") (width 0.2032) (tstamp ae78fb03-f3e0-4acc-ade3-377a34235a11))
|
||||
(fp_line (start -35.61 4.1) (end 35.61 4.1) (layer "F.SilkS") (width 0.2032) (tstamp d5ba9664-cc00-4c31-90e2-09d807b13671))
|
||||
(fp_line (start -35.61 4.1) (end -34.81 3.3) (layer "F.SilkS") (width 0.2032) (tstamp e4ac115e-9dab-4378-bd06-56549077f103))
|
||||
(fp_line (start 34.81 3.3) (end 1.9 3.3) (layer "F.SilkS") (width 0.2032) (tstamp edce6cab-fa11-4ca3-a0b3-6ef2d4b2d390))
|
||||
(fp_line (start 35.61 -4.1) (end -35.61 -4.1) (layer "F.SilkS") (width 0.2032) (tstamp f10ab846-6d45-492e-9ad2-760c29b98791))
|
||||
(pad "1" thru_hole roundrect (at -30.48 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp e9916782-f163-46d2-b8e7-bb22bfa7e2ea))
|
||||
(pad "2" thru_hole roundrect (at -30.48 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 98ee6c1b-84d5-4c0f-a3a3-5fc333ee1a20))
|
||||
(pad "3" thru_hole roundrect (at -27.94 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp a37a96e8-ef70-43c9-83cd-aa0adc092ac6))
|
||||
(pad "4" thru_hole roundrect (at -27.94 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 56c5df4f-1eb5-487c-95be-5fd97e614ae5))
|
||||
(pad "5" thru_hole roundrect (at -25.4 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp e701a5bb-d1dd-4478-9b9e-e2eb6df9ac3b))
|
||||
(pad "6" thru_hole roundrect (at -25.4 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 11ddc590-9bb1-4938-ace7-57fd7c4570f8))
|
||||
(pad "7" thru_hole roundrect (at -22.86 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 3eb54c20-5c6d-44d3-ae45-0667c67eff80))
|
||||
(pad "8" thru_hole roundrect (at -22.86 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 7f0cda5e-91af-49ea-b825-244f33f46fdc))
|
||||
(pad "9" thru_hole roundrect (at -20.32 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 516baf97-166a-4606-a123-35849d375f9f))
|
||||
(pad "10" thru_hole roundrect (at -20.32 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 4d9d6954-6af7-45d1-8068-a343f5ad1f44))
|
||||
(pad "11" thru_hole roundrect (at -17.78 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 4d2eed1d-1788-4376-8b7e-0c8e32d980cf))
|
||||
(pad "12" thru_hole roundrect (at -17.78 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 9ddc5228-821e-4164-b084-59746e77db0f))
|
||||
(pad "13" thru_hole roundrect (at -15.24 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 46e5bbe9-f639-4fdc-b2f7-3f8e943da616))
|
||||
(pad "14" thru_hole roundrect (at -15.24 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp a89809b2-4788-4901-b25d-0587905e1c9f))
|
||||
(pad "15" thru_hole roundrect (at -12.7 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 7c6ed292-8bcd-469a-b917-83ec1043d403))
|
||||
(pad "16" thru_hole roundrect (at -12.7 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 733b2af5-63ec-477e-85ae-e61450e7cce9))
|
||||
(pad "17" thru_hole roundrect (at -10.16 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 0d0b2f24-c6ac-428f-8785-b991f677f993))
|
||||
(pad "18" thru_hole roundrect (at -10.16 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp cca1c68e-0d7f-4832-9f61-3e37dafe48b0))
|
||||
(pad "19" thru_hole roundrect (at -7.62 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp b6f4d3f4-b9b8-4338-8e89-a06cc704734e))
|
||||
(pad "20" thru_hole roundrect (at -7.62 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 20cd7e06-6b1c-41bd-b699-8bfd2f0c7fab))
|
||||
(pad "21" thru_hole roundrect (at -5.08 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 7108a223-c3e7-42f5-9777-06ce8fc5a1ba))
|
||||
(pad "22" thru_hole roundrect (at -5.08 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
(pad "25" thru_hole roundrect (at 0 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
(solder_mask_margin 0.1016) (tstamp 3ce3d843-076c-4add-a6e9-e40d6b5c828c))
|
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(pad "31" thru_hole roundrect (at 7.62 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
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||||
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|
||||
(pad "32" thru_hole roundrect (at 7.62 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
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|
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(solder_mask_margin 0.1016) (tstamp 18a64e4d-4850-4d39-b4ea-e971258daa1e))
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|
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||||
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|
||||
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|
||||
(pad "36" thru_hole roundrect (at 12.7 -1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
|
||||
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|
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|
||||
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|
||||
(chamfer_ratio 0.2928932188) (chamfer top_left top_right bottom_left bottom_right)
|
||||
(solder_mask_margin 0.1016) (tstamp 81470f36-9f63-4475-b10f-63bbd356236d))
|
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|
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|
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(pad "39" thru_hole roundrect (at 17.78 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
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||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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(solder_mask_margin 0.1016) (tstamp 38795d9d-95d0-49a9-960b-4bf0791e42db))
|
||||
(pad "47" thru_hole roundrect (at 27.94 1.27) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
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||||
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|
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|
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|
||||
)
|
||||
44
Appletini/PCB_v1.pretty/1X02.kicad_mod
Normal file
44
Appletini/PCB_v1.pretty/1X02.kicad_mod
Normal file
@@ -0,0 +1,44 @@
|
||||
(footprint "1X02" (version 20211014) (generator pcbnew)
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||||
(layer "F.Cu")
|
||||
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|
||||
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||||
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||||
)
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(fp_text value ">VALUE" (at -2.54 3.175) (layer "F.SilkS")
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||||
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||||
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||||
152
Appletini/PCB_v1.pretty/A2-50PIN-SL4-7.kicad_mod
Normal file
152
Appletini/PCB_v1.pretty/A2-50PIN-SL4-7.kicad_mod
Normal file
@@ -0,0 +1,152 @@
|
||||
(footprint "A2-50PIN-SL4-7" (version 20211014) (generator pcbnew)
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||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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||||
154
Appletini/PCB_v1.pretty/CAP-PTH-SMALL-KIT.kicad_mod
Normal file
154
Appletini/PCB_v1.pretty/CAP-PTH-SMALL-KIT.kicad_mod
Normal file
@@ -0,0 +1,154 @@
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||||
(footprint "CAP-PTH-SMALL-KIT" (version 20211014) (generator pcbnew)
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||||
(layer "F.Cu")
|
||||
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|
||||
(descr "<h3>CAP-PTH-SMALL-KIT</h3>\nCommonly used for small ceramic capacitors. Like our 0.1uF (http://www.sparkfun.com/products/8375) or 22pF caps (http://www.sparkfun.com/products/8571).<br>\n<br>\n<b>Warning:</b> This is the KIT version of this package. This package has a smaller diameter top stop mask, which doesn't cover the diameter of the pad. This means only the bottom side of the pads' copper will be exposed. You'll only be able to solder to the bottom side.")
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||||
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60
Appletini/PCB_v1.pretty/PROTOBOARD.kicad_mod
Normal file
60
Appletini/PCB_v1.pretty/PROTOBOARD.kicad_mod
Normal file
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(footprint "PROTOBOARD" (version 20211014) (generator pcbnew)
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44
Appletini/PCB_v1.pretty/PROTOBUS.kicad_mod
Normal file
44
Appletini/PCB_v1.pretty/PROTOBUS.kicad_mod
Normal file
@@ -0,0 +1,44 @@
|
||||
(footprint "PROTOBUS" (version 20211014) (generator pcbnew)
|
||||
(layer "F.Cu")
|
||||
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|
||||
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|
||||
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(tstamp 5da1c746-b875-4905-b435-da525da1b913)
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)
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(fp_text value "" (at 0 0) (layer "F.SilkS")
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|
||||
(tstamp df74fe5f-8041-4106-87f8-bdb606b35124)
|
||||
)
|
||||
(pad "GND@1" thru_hole oval (at 5.08 0) (size 3.016 1.508) (drill 1) (layers *.Cu *.Mask)
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||||
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||||
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||||
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||||
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||||
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|
||||
3
Appletini/fp-lib-table
Normal file
3
Appletini/fp-lib-table
Normal file
@@ -0,0 +1,3 @@
|
||||
(fp_lib_table
|
||||
(lib (name "PCB_v1")(type "KiCad")(uri "$(KIPRJMOD)/PCB_v1.pretty")(options "")(descr ""))
|
||||
)
|
||||
Reference in New Issue
Block a user